Design And Simulation Of Computer Piagonistic System (A Case Study Of Ibm Pg)

DESIGN AND SIMULATION OF COMPUTER PIAGONISTIC SYSTEM (A CASE STUDY OF IBM PG)

Computer Piagonistic System

TABLE OF CONTENTS

Title page

Abstract

Organization of work

List of figures

List of table

Table of content

CHAPTER ONE

INTRODUCTION

1.0            Statement of problem

1.1     purpose of study

1.2     Aims and objectives

1.3            Scope

1.4            Limitations

1.5            Definitions of terms

CHAPTER TWO

Literature Review

CHAPTER THREE

Description and Analysis of the Existing System

Organization structure

Objectives of the existing system

CHAPTER FOUR

Design of the New System

Output specification and design

Input specification and design

File design

Procedure chart

System flow chart

System requirement

CHAPTER FIVE  

Implementation

Program flowchart

CHAPTER SIX

Documentation

CHAPTER SEVEN

Recommendation and Conclusion

7.1     Recommendation

7.2     Conclusion

Reference

LIST OF FIGURES

FIG 1.0       and gate diagram

Fig 1.1        capacitor diagram

Fig 1.2        seven segment diagram

Fig 3.01      block schematic diagram of an electronic dice display

Fig 3.02      block schematic diagram of an audio unit

Fig 3.03      555 timer schematic circuit diagram

Fig 3.04      555 timer block diagram

Fig 3.05      555 timer configuration

Fig 3.06      pin-out connection of a 555 timer

Fig 3.07a    555 timers in astable mode

Fig 3.07b    timing diagram

Fig 3.08      Jk flip flop symbol

Fig 3.09      delay flip-flop from Jk flip-flop

Fig 3.10a    delay flip-flop from JK flip-flop

Fig 3.10b    D flip-flop timing diagram

Fig 3.11      D type flip-flop in TTL

Fig 3.12      Quad-and gate symbol

Fig 3.13a    Circuit block diagram of a digital counter

Fig 3.13b    Output wave forms

Fig 3.14a    circuit block diagram of mod 10 counter

Fig 3.14b    output wave forms

Fig 3.15      Mod 6 counter using decade counter

Fig 3.16      functional logic diagram of BCD to decimal decoder

Fig 3.17      seven segment display layout arrangement

Fig 3.18      seven segment display connections

Fig 3.19      BCD to seven segment block diagram

Fig 3.20      7447 BCD to seven segment decoder driver functional

Fig 4.01      top view of 7414

Fig 4.02      counter configuration for the 7490A

Fig 4.03      top view of 7474

Fig 4.04      top view of SN 7447

Fig 4.05      top view of common unode display

Fig 5.01      output wave of 555 timers

LIST OF TABLE

Table 3.1 time table for sK flip-flop

Table 3.2 delay flip-flop forms flip-flop

Table 3.4 and logic gate truth table

Table 3.5 table of counter output in various forms.

Table 3.7 bid to seven segment decoder truth table

Table 4.1a BCD count sequence

Table 5.0 procedure chart

Table 5.1 system flowchart

Table 6.0 program design

Table 6.1 program flowchart

 

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